AI compute: GPUs, neuromorphic and photonic chips

How do GPUs, neuromorphic chips, photonic computing and optical interconnects compare on the energy evidence, precision or programmability limits, and deployment stage reported in their sources?

This table sets one GPU vendor specification against research results for neuromorphic chips, photonic computing and optical interconnects. Most figures for the other rows come from single lab systems, company claims or the authors' own devices, so they are not directly comparable with each other or with the GPU specification.

AI compute: GPUs, neuromorphic and photonic chips. Each cell shows a value, how well it is evidenced, and its sources.
Option	What it does wellQualitative: the workload or property the cited sources report as a strength, with the test conditions where a figure is given.	Energy efficiency evidenceReported power or energy with units (mW, W, pJ/bit, pJ per operation or frames per second per watt), labelled as lab, preprint, vendor or specification.	Precision or programmability limitsQualitative: number formats, analogue noise, programming tools or scope limits reported in the cited sources.	Deployment stageQualitative: how far the approach has moved from lab work to commercial use, as stated in the cited sources.
GPUs	Dense FP16 Tensor Core throughput of 312 TFLOPS for the A100 80GB PCIe (vendor peak specification, not a measured workload).Reported, unverified[1]	Rated board power of 300 W for the A100 80GB PCIe, stated alongside the 312 TFLOPS figure (vendor specification; no measured workload energy in the source).Reported, unverified[1]	Supports FP64, TF32, BF16, FP16 and INT8 Tensor Core formats (vendor specification table).Reported, unverified[1]	Commercial vendor product with published specifications. The page gives no launch date and no deployment counts.Reported, unverified[1]
Neuromorphic chips	IBM's TrueNorth consumed 63 mW with 400 x 240 pixel video input at 30 frames per second (2014 lab chip; the abstract names multiobject detection and classification as target applications).Demonstrated[2]	IBM's NorthPole (2023, lab benchmark) reported 25 times more frames per second per watt than a GPU on ResNet50, on a comparable 12 nm process.Demonstrated[3]	NorthPole is described as a low-precision inference architecture. The abstract reviewed does not report accuracy figures.Demonstrated[3]	Research chips and the Hala Point research system. Its 1,152 Loihi 2 processors arrived at Sandia National Laboratories in early 2024; the photo caption gives 1 February (per Sandia's Lab News article of 18 April 2024).Reported, unverified[4]
Photonic computing	Wu and colleagues (2025) trained an on-chip photonic neural network in situ and ran its convolutional and fully connected layers on light, on small image tasks.Demonstrated[5]	No reliable public figure	Wu and colleagues (2025) report 96% accuracy on two-class fashion image classification and 94% on four-class handwritten digit classification, with performance said to be well maintained under partially coherent illumination (abstract figures). The abstract does not report results on large contemporary models.Demonstrated[5]	Research prototypes. Hua and colleagues (Nature, 2025) report a photonic accelerator with more than 16,000 photonic components, co-integrated with an electronics chip, and ultralow latency on heuristic solver tests for Ising problems at up to 1 GHz.Demonstrated[6]
Optical interconnects	Tu and colleagues (2019) report a 32 x 32 silicon photonic switch at about 0.8 pJ per bit on a 100 Gb/s light path, from the authors' own device.Reported, unverified[8]	Tian and colleagues (2024) give about 15 to 20 pJ/bit for pluggable optical modules, attributed to Broadcom data, and about 5 to 10 pJ/bit for co-packaged optics, a figure the review quotes from other sources.Reported, unverified[7]	Moves data rather than computing, so arithmetic precision does not apply. A simulation by the CPO standard working group gives 151.76 °C for a switch chip with 16 co-packaged optics modules at 5 m/s airflow, which the review says makes normal operation nearly impossible.Reported, unverified[7]	Early stage of industrialisation, according to Tian and colleagues (2024). Cisco showed a co-packaged optics router demonstration at OFC 2023 with 'up to' power savings, and VCSEL-based co-packaged optics remain at research and development stage.Reported, unverified[9][7]

AI compute: GPUs, neuromorphic and photonic chips. Each cell shows a value, how well it is evidenced, and its sources.

Option

What it does wellQualitative: the workload or property the cited sources report as a strength, with the test conditions where a figure is given.

Energy efficiency evidenceReported power or energy with units (mW, W, pJ/bit, pJ per operation or frames per second per watt), labelled as lab, preprint, vendor or specification.

Precision or programmability limitsQualitative: number formats, analogue noise, programming tools or scope limits reported in the cited sources.

Deployment stageQualitative: how far the approach has moved from lab work to commercial use, as stated in the cited sources.

GPUs

Dense FP16 Tensor Core throughput of 312 TFLOPS for the A100 80GB PCIe (vendor peak specification, not a measured workload).Reported, unverified[1]

Rated board power of 300 W for the A100 80GB PCIe, stated alongside the 312 TFLOPS figure (vendor specification; no measured workload energy in the source).Reported, unverified[1]

Supports FP64, TF32, BF16, FP16 and INT8 Tensor Core formats (vendor specification table).Reported, unverified[1]

Commercial vendor product with published specifications. The page gives no launch date and no deployment counts.Reported, unverified[1]

Neuromorphic chips

IBM's TrueNorth consumed 63 mW with 400 x 240 pixel video input at 30 frames per second (2014 lab chip; the abstract names multiobject detection and classification as target applications).Demonstrated[2]

IBM's NorthPole (2023, lab benchmark) reported 25 times more frames per second per watt than a GPU on ResNet50, on a comparable 12 nm process.Demonstrated[3]

NorthPole is described as a low-precision inference architecture. The abstract reviewed does not report accuracy figures.Demonstrated[3]

Research chips and the Hala Point research system. Its 1,152 Loihi 2 processors arrived at Sandia National Laboratories in early 2024; the photo caption gives 1 February (per Sandia's Lab News article of 18 April 2024).Reported, unverified[4]

Photonic computing

Wu and colleagues (2025) trained an on-chip photonic neural network in situ and ran its convolutional and fully connected layers on light, on small image tasks.Demonstrated[5]

No reliable public figure

Wu and colleagues (2025) report 96% accuracy on two-class fashion image classification and 94% on four-class handwritten digit classification, with performance said to be well maintained under partially coherent illumination (abstract figures). The abstract does not report results on large contemporary models.Demonstrated[5]

Research prototypes. Hua and colleagues (Nature, 2025) report a photonic accelerator with more than 16,000 photonic components, co-integrated with an electronics chip, and ultralow latency on heuristic solver tests for Ising problems at up to 1 GHz.Demonstrated[6]

Optical interconnects

Tu and colleagues (2019) report a 32 x 32 silicon photonic switch at about 0.8 pJ per bit on a 100 Gb/s light path, from the authors' own device.Reported, unverified[8]

Tian and colleagues (2024) give about 15 to 20 pJ/bit for pluggable optical modules, attributed to Broadcom data, and about 5 to 10 pJ/bit for co-packaged optics, a figure the review quotes from other sources.Reported, unverified[7]

Moves data rather than computing, so arithmetic precision does not apply. A simulation by the CPO standard working group gives 151.76 °C for a switch chip with 16 co-packaged optics modules at 5 m/s airflow, which the review says makes normal operation nearly impossible.Reported, unverified[7]

Early stage of industrialisation, according to Tian and colleagues (2024). Cisco showed a co-packaged optics router demonstration at OFC 2023 with 'up to' power savings, and VCSEL-based co-packaged optics remain at research and development stage.Reported, unverified[9][7]

What the table shows

The two neuromorphic energy cells come from peer-reviewed lab results with different benchmarks: TrueNorth reports power for a video input, and NorthPole reports frames per second per watt against a GPU on ResNet50.
The photonic row has no energy figure. Its accuracy results are on small image tasks.
The optical interconnect energy cell compares pluggable modules at about 15 to 20 pJ/bit with co-packaged optics at about 5 to 10 pJ/bit, as quoted in a 2024 review.
Neuromorphic, photonic and optical interconnect entries are at research or early industrialisation stage, while the GPU entry is a vendor product with specifications only.

Read with care

The GPU figures are vendor peak specifications for one A100 variant. They were not measured on the benchmarks used for the neuromorphic or photonic results.
Lab figures use selected benchmarks, single devices or the authors' own systems. Several are company claims or the authors' own work, as labelled in each cell.
The NorthPole comparison is against a GPU that the cited abstract does not name, on a 12 nm process.
Optical interconnects move data rather than compute, so this row gives context for the photonic rows and is not a like-for-like alternative to processors.
The photonic energy cell is empty because the full text of the 2025 paper was not reachable during review, so its energy values were not checked.

Sources

other
NVIDIA A100 Tensor Core GPU
NVIDIA, 2026. Accessed 21 Oct 2026.
peer reviewed paper
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla, et al.. Science, 7 Aug 2014. Accessed 21 Oct 2026.
peer reviewed paper
Neural inference at the frontier of energy, space, and time
Dharmendra S. Modha, et al.. Science, 19 Oct 2023. Accessed 21 Oct 2026.
news
1.15 billion artificial neurons arrive at Sandia
Neal Singer. Sandia National Laboratories (Sandia Lab News), 18 Apr 2024. Accessed 21 Oct 2026.
peer reviewed paper
Scaling up for end-to-end on-chip photonic neural network inference
Bo Wu, Chaoran Huang, et al.. Light: Science & Applications, 17 Sept 2025. Accessed 21 Oct 2026.
peer reviewed paper
An integrated large-scale photonic accelerator with ultralow latency
Hua, Divita, Yu et al.. Nature, 9 Apr 2025. Accessed 21 Oct 2026.
review article
Progress in Research on Co-Packaged Optics
Wenchao Tian, et al.. Micromachines (MDPI), 29 Sept 2024. Accessed 21 Oct 2026.
review article
State of the Art and Perspectives on Silicon Photonic Switches
Xin Tu, et al.. Micromachines (MDPI), 13 Jan 2019. Accessed 21 Oct 2026.
company announcement
Cisco Demonstrates Co-packaged Optics (CPO) System at OFC 2023
Anthony Torza. Cisco Systems (blog), 7 Mar 2023. Accessed 21 Oct 2026.