Neuromorphic computing chips

In plain language

Most computers keep memory and processing apart and move data back and forth constantly, which costs time and energy. The brain works differently: billions of neurons store and process information in the same place and only send a signal when something changes.

Neuromorphic chips borrow these ideas. They contain many small processing units that act like neurons and send brief pulses to each other. The hope is to run AI and sensing tasks using far less electricity, especially in devices such as robots, sensors and phones.

Technical explanation

Carver Mead set out the idea of neuromorphic electronic systems in a 1990 paper, and the field began with silicon circuits that mimic biological neural processes. Modern digital neuromorphic chips usually implement spiking neural networks: each core holds a set of neuron models and their synaptic weights, and neurons exchange small event packets (spikes) over an on-chip network only when they fire. This event-driven operation and the close placement of memory and compute are the main sources of claimed energy savings.

IBM's TrueNorth (2014) packed 4,096 neurosynaptic cores with 1 million neurons and 256 million synapses into 5.4 billion transistors and ran real-time video object detection at 63 mW. Intel's Loihi (2018) included programmable on-chip learning rules, and its successor Loihi 2 is the basis of Hala Point, a 1,152-chip research system delivered to Sandia National Laboratories in 2024. Other research platforms, such as the SpiNNaker project, have also been built to run large spiking network models.

A related branch keeps the brain-inspired idea of memory beside compute but drops spikes. IBM's NorthPole (2023) is a low-precision inference chip with no off-chip memory that reported higher energy efficiency and lower latency than a GPU on a comparable process for image classification.

Research has also moved from simulation toward hardware results for scientific and training workloads. A 2025 paper in Nature Machine Intelligence, first posted as an arXiv preprint in January 2025, maps the sparse interactions between neighbouring mesh elements of the finite element method onto small groups of spiking neurons running on Intel's Loihi 2. The preprint reports accuracy and scaling comparable to conventional methods for the Poisson equation but gives no quantitative energy or speed figures. A 2026 Nature Communications paper, first posted as a preprint in November 2024 and published online in March 2026, describes a multi-core design with separate forward, backpropagation and weight-gradient engines for training spiking networks directly. The preprint reports 1.05 TFLOPS/W at FP16 for a 28 nm process, but its abstract does not say whether that figure was measured on fabricated silicon. FPGA demonstrations of the design include a 20-core configuration for deep spiking network training and a five-worker federated learning setup.

Key open problems are programming tools, training methods for spiking networks that match deep learning accuracy, and showing clear advantages on real workloads rather than selected benchmarks.

What the evidence says

Each statement is typed by the strength of its evidence and linked to the source that supports it.

Limitations and open problems

• Software tools and programming models are far less mature than those for CPUs and GPUs, so few developers can use the hardware.
• Training spiking neural networks to match the accuracy of conventional deep learning remains an active research problem.
• Reported efficiency gains are usually measured on selected benchmarks and often supplied by the chip makers themselves.
• Large systems such as Hala Point are research platforms rather than commercially deployed products.
• Different chips use incompatible architectures, which makes fair comparison and code portability difficult.
• Results for on-chip training so far rest on a 28 nm efficiency figure whose measurement basis the abstract does not state, and on FPGA prototypes, not on a shipped product.
• The sources reviewed here test on-device learning on benchmark tasks only. They do not show that a device can keep learning safely in uncontrolled settings, avoid forgetting earlier skills or resist corrupted data.

Possible future uses

Product concepts: Offline pocket AI assistant

Timeline

1. 1990Carver Mead sets out the concept of neuromorphic electronic systems in Proceedings of the IEEE. Sources: [1]
2. May 2014The SpiNNaker many-core neuromorphic project is described in Proceedings of the IEEE. Sources: [3]
3. Aug 2014IBM publishes TrueNorth, a million-neuron spiking chip, in Science. Sources: [2]
4. Jan 2018Intel describes Loihi, a neuromorphic manycore processor with on-chip learning. Sources: [4]
5. Oct 2023IBM publishes NorthPole, a brain-inspired inference chip with memory and compute intertwined on chip. Sources: [6]
6. Feb 2024Intel delivers Hala Point, a 1.15 billion neuron Loihi 2 system, to Sandia National Laboratories. Sources: [7]
7. Nov 2024A preprint describes a multi-core neuromorphic architecture for directly training deep spiking networks, with forward, backpropagation and weight-gradient engines in each core. Sources: [11]
8. Jan 2025Theilman and Aimone post a preprint on solving sparse finite element problems on neuromorphic hardware, run on Intel's Loihi 2. Sources: [8]
9. Nov 2025Theilman and Aimone's finite element work is published online in Nature Machine Intelligence on 13 November 2025. Sources: [9]
10. Mar 2026Nature Communications publishes online a multi-core neuromorphic architecture for training deep spiking neural networks, on 25 March 2026. Sources: [10]

Futures this could help bring about

How far away?

Cameras that see like eyes

Pilots · 7 of 10 steps done

How far away?

Computer chips that work like brains

Pilots · 4 of 8 steps done

Related breakthroughs

• Hala Point neuromorphic system with 1.15 billion artificial neurons delivered to Sandia (18 Apr 2024)

Glossary

Spiking neural network

A neural network in which artificial neurons communicate with brief on-off pulses (spikes) rather than continuous numbers.

Event-driven

Computing that only does work when an input changes, instead of on every clock tick.

Synapse

In neuromorphic hardware, a stored connection weight that sets how strongly one neuron affects another.

Von Neumann bottleneck

The cost in time and energy of moving data between separate memory and processor, which neuromorphic designs try to avoid.

On-chip learning

The ability of a chip to update its network's weights itself while running, without retraining on a separate computer.

Finite element method (FEM)

A numerical method that approximates solutions to physical equations by dividing a region into smaller elements.

Fixed-point arithmetic

A number format with a fixed scaling point. It can use less hardware than floating point but may add rounding error.

FPGA

A reconfigurable chip used to prototype digital circuits. Its power and speed do not automatically predict those of a purpose-built chip.

Federated learning

Training a shared model across separate devices or data holders, keeping the data on each device and exchanging only model updates.

Sources

1. peer reviewed paper
   Neuromorphic electronic systems
   Carver Mead. Proceedings of the IEEE, 1990. DOI: 10.1109/5.58356. Accessed 20 Oct 2026.
2. peer reviewed paper
   A million spiking-neuron integrated circuit with a scalable communication network and interface
   Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza et al.. Science, 7 Aug 2014. DOI: 10.1126/science.1254642. Accessed 20 Oct 2026.
3. peer reviewed paper
   The SpiNNaker Project
   Steve B. Furber, Francesco Galluppi, Steve Temple et al.. Proceedings of the IEEE, May 2014. DOI: 10.1109/JPROC.2014.2304638. Accessed 20 Oct 2026.
4. peer reviewed paper
   Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
   Mike Davies, Narayan Srinivasa, Tsung-Han Lin et al.. IEEE Micro, Jan 2018. DOI: 10.1109/MM.2018.112130359. Accessed 20 Oct 2026.
5. review article
   Towards spike-based machine intelligence with neuromorphic computing
   Kaushik Roy, Akhilesh Jaiswal, Priyadarshini Panda. Nature, 27 Nov 2019. DOI: 10.1038/s41586-019-1677-2. Accessed 20 Oct 2026.
6. peer reviewed paper
   Neural inference at the frontier of energy, space, and time
   Dharmendra S. Modha, Filipp Akopyan, Alexander Andreopoulos et al.. Science, 19 Oct 2023. DOI: 10.1126/science.adh1174. Accessed 20 Oct 2026.
7. news
   1.15 billion artificial neurons arrive at Sandia
   Neal Singer. Sandia National Laboratories (Sandia Lab News), 18 Apr 2024. Accessed 20 Oct 2026.
8. preprint
   Solving Sparse Finite Element Problems on Neuromorphic Hardware
   Bradley H. Theilman, James B. Aimone. arXiv, 17 Jan 2025. DOI: 10.48550/arXiv.2501.10526. Accessed 21 Oct 2026.
9. peer reviewed paper
   Solving sparse finite element problems on neuromorphic hardware
   Bradley H. Theilman, James B. Aimone. Nature Machine Intelligence, 13 Nov 2025. DOI: 10.1038/s42256-025-01143-2. Accessed 21 Oct 2026.
10. peer reviewed paper
    A highly energy-efficient multi-core neuromorphic architecture for training deep spiking neural networks
    Mingjing Li, Huihui Zhou, Xiaofeng Xu et al.. Nature Communications, 25 Mar 2026. DOI: 10.1038/s41467-026-70586-x. Accessed 21 Oct 2026.
11. preprint
    A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training
    Mingjing Li, Huihui Zhou, Xiaofeng Xu et al.. arXiv, 26 Nov 2024. DOI: 10.48550/arXiv.2412.05302. Accessed 21 Oct 2026.

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