Computer chips designed mostly by AI

How far are we from computer chips being designed mostly by AI?

AI tools already help with parts of chip design, and a small processor was designed through conversation with a large language model and sent for fabrication. No source measures how much of chip design AI now does. Google's AlphaChip method for placing circuit blocks is disputed: its authors say critics did not test it as described, and critics report that it did not beat stronger baselines. Synopsys says its new verification agent runs up to 50 times faster, but the baseline is not described and the tool was still being evaluated by customers in July 2026. Human engineers still define design intent, as the Synopsys release describes, so a chip designed mostly by AI is not yet shown.

AI illustration · Illustrative scene, not a photograph of the specific device or experiment.
WHERE WE AREPilots

Close. Early pilots are running in the real world.

Pilot. Several AI tools are being tested with customers, and one small processor was taped out after a conversation with a large language model. The vendor and author figures are not independently checked. The main placement method is disputed: its authors say critics did not run it as described, and critics say it did not beat stronger baselines. No source gives the share of chip design work done by AI, so the technology is not yet at scaling.

The tech tree

Everything recorded on Vrulum that this future needs, oldest foundations at the top and the goal at the bottom. Lines show what each step requires.

What it takes: Computer chips designed mostly by AI Unlocked Being researched Locked
  1. 2021AI-assisted chip designPilot and early commercial Unlocked.
  1. 2020AI placement method reported to match human layoutsDone Unlocked.
  2. 2023Independent re-evaluations test the placement method against stronger baselinesIn progress Being researched.
  3. 2023Small processor designed through conversation with an LLM and fabricatedDone Unlocked.
  4. 2026AI agents for verification and debug offered by EDA vendorsIn progress Being researched.
  5. Date not recordedPublished share of chip design work done by AI, with a stated methodNot started Locked.
  6. Date not recordedCommercial-scale chip with most of its logic written by AI and checked by an independent reviewNot started Locked.
  1. GoalComputer chips designed mostly by AIGoalRequires: AI-assisted chip design, AI placement method reported to match human layouts, Independent re-evaluations test the placement method against stronger baselines, Small processor designed through conversation with an LLM and fabricated, AI agents for verification and debug offered by EDA vendors, Published share of chip design work done by AI, with a stated method, Commercial-scale chip with most of its logic written by AI and checked by an independent review. Locked.

The road so far

2 of 6 steps done, 2 in progress.

  1. Done · 22 Apr 2020AI placement method reported to match human layouts

    A 2020 preprint by Google researchers describes a reinforcement learning method that places chip blocks. Its abstract says the method generates placements in under six hours, with results 'superhuman or comparable on modern accelerator netlists'. The abstract gives no power, performance or area figures. The 2021 Nature version was not opened for this record. [1]

  2. In progress · Feb 2023Independent re-evaluations test the placement method against stronger baselines

    Cheng, Kahng and colleagues (first posted February 2023) compared the method with a stronger simulated annealing baseline. Their March 2026 version says that Google's scalability and pre-training methodology remain unconfirmed and open for the research community. Markov's 2023 preprint, a review of earlier evaluations, concludes that the method trails human designers, simulated annealing and commercial software. Goldie, Mirhoseini and Dean's November 2024 reply says critics skipped pre-training, used far fewer compute resources and did not train to convergence. The two sides disagree on the test conditions, and no independent result settles the question. [2][3][4]

  3. Done · May 2023Small processor designed through conversation with an LLM and fabricated

    A 2023 preprint by Blocklove, Garg, Karri and Pearce describes an 8-bit accumulator processor co-designed with a large language model and a hardware engineer. The design was taped out on a Skywater 130nm shuttle. The authors say it is likely the first tape-out of wholly AI-written hardware description code. The paper reports no gate count, die size or number of attempts, and the design is small. [5]

  4. In progress · 26 Jul 2026AI agents for verification and debug offered by EDA vendors

    On 26 July 2026 Synopsys announced an autonomous design verification agent, demonstrated at DAC. It claims up to 50 times faster time to validated RTL and an additional 20 percent coverage improvement, both compared with workflows not using its technology. The release gives no design, workload or baseline for these figures. Customers are evaluating the capabilities, with availability planned for the second half of 2026. [6]

  5. Not startedPublished share of chip design work done by AI, with a stated method

    No source reviewed gives a share of chip design work, RTL or layout done by AI, and none defines how such a share would be counted. The Synopsys release describes engineers defining design intent and goals in natural language, but it gives no proportion. [6]

  6. Not startedCommercial-scale chip with most of its logic written by AI and checked by an independent review

    The largest AI-designed example in the sources reviewed is the small 2023 processor. No commercial-scale chip with most of its logic written by AI, and checked under a stated review process, has been reported in the sources reviewed. [5]

Why it matters

Chip design is slow and costly, and a fault found after fabrication can be expensive to fix. If AI tools can carry most of the routine work, design teams could test more options and finish sooner. The same tools would also raise questions about how to check a design that no engineer fully wrote or reviewed.

What stands in the way

  • No source measures how much of chip design AI does, so there is no baseline to track progress against.
  • The main placement result is disputed. Scalability and pre-training methodology remain unconfirmed in the 2026 assessment, and the two sides disagree on fair comparison conditions.
  • Vendor claims of speed-up and coverage gain do not state the design, workload or baseline used.
  • The best-documented AI-designed chip is small. Scaling to a complex chip raises verification effort, which the sources reviewed do not quantify.
  • Human engineers still define design intent, and the sources reviewed describe no way to check a design that no engineer fully wrote or reviewed.

Signals to watch

  • Independent results on a shared, public set of placement tasks with pre-stated baselines and compute budgets.
  • A chip vendor or design team publishing the share of its RTL or layout produced by AI, with a defined counting method.
  • Synopsys, Cadence or Siemens reporting customer results for their agent tools with the design, workload and baseline stated.
  • A tape-out of a complex chip where AI produced most of the logic, with the human edits recorded.
  • Peer-reviewed versions of the placement disputes, including any response to the 2023 critiques.

Sources

  1. preprint
    Chip Placement with Deep Reinforcement Learning
    Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan et al.. arXiv, 22 Apr 2020.
  2. preprint
    An Updated Assessment of Reinforcement Learning for Macro Placement
    Chung-Kuan Cheng, Andrew Kahng, Sayak Kundu et al.. arXiv, 21 Feb 2023.
  3. preprint
    The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement
    Igor L. Markov. arXiv, 16 Jun 2023.
  4. preprint
    That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design
    Anna Goldie, Azalia Mirhoseini, Jeff Dean. arXiv, 15 Nov 2024.
  5. preprint
    Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
    Jason Blocklove, Siddharth Garg, Ramesh Karri et al.. arXiv, 22 May 2023.
  6. company announcement
    Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology
    Synopsys, 26 Jul 2026.

Last reviewed 22 Oct 2026.