An integrated photonic accelerator with more than 16,000 components reduces computation time for Ising-problem solvers

What was demonstrated
Hua and colleagues report a large-scale integrated photonic accelerator with more than 16,000 photonic components, built to perform linear matrix multiply-accumulate operations at up to 1 GHz, with about 3 ns latency per cycle. The authors co-integrated electronic logic, memory and control chips with the photonics using 2.5D hybrid advanced packaging. They report that the low latency reduces computation time for heuristic solvers of hard Ising problems.
Why it matters
The paper reports a packaged photonic system of more than 16,000 components with very short per-cycle latency on a hard optimisation workload. This suggests photonic matrix hardware can be built at this scale, though the abstract does not show it is a general-purpose accelerator.
Caveats
- The demonstrated workload is heuristic Ising-problem solving. This does not show general speed or energy gains for AI model training or inference.
- The abstract reviewed gives no energy figure and no direct comparison with GPUs. Any such claims need the full paper.
- Independent replication has not been reported in the sources reviewed.
- Latency per cycle is a hardware figure, but overall system latency and throughput depend on the host interface and problem setup, which the abstract does not fully describe.
Technology profiles
Sources
- peer reviewed paper
An integrated large-scale photonic accelerator with ultralow latency
Shiyue Hua, Erwan Divita, Shanshan Yu et al.. Nature, 9 Apr 2025. DOI: 10.1038/s41586-025-08786-6. - other
An integrated large-scale photonic accelerator with ultralow latency (repository record)
Shiyue Hua, Erwan Divita, Shanshan Yu et al.. Institute of Science and Technology Austria (ISTA) Research Explorer, 9 Apr 2025. DOI: 10.1038/s41586-025-08786-6.
Last reviewed 21 Oct 2026.